Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a new SEU mode in an on n-channel device is presented.