Threshold LET for SEU induced by low energy ions [in CMOS memories]

Simulations to determine the threshold LET as a function of the length of the ion track are consistent with there being two regions of charge collection. In the top layer which contains the depletion region all the charge generated is collected in time to upset the device. In the next layer, 10% to 20% of the charge generated is collected and contributes to upsetting the device. This second layer of partial charge collection may significantly impact the accuracy of SEU predictions involving low-energy neutrons and protons. A simple method of including this contribution in calculations is proposed.