Impact of floating dot distribution on memory characteristics of self-aligned dots-on-nanowire memory

A nanowire memory device with self-aligned Si nanoscale floating dots has been fabricated to overcome the tradeoff between retention time and programming speed. The dependence of memory characteristics on the dot number and distribution have been systematically analyzed experimentally and numerically to provide design guidelines for optimizing device performance. Distributing multiple floating dots in series along the channel with each dot covering the whole channel width is essential for better retention characteristics, while maintaining similar programming characteristics without increasing the operating voltage. The spacing between dots is also an important factor for optimizing device performance. Taking into account the compatibility of the fabrication process with that of the conventional flash-type nonvolatile memory, the self-aligned dots-on-nanowire memory with multiple floating dots distributed in series along a nanowire channel is the best structure for high-performance memory.