Heat removal and power delivery have become two major reliability concerns in 3-D integrated circuit (IC) technology. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic channel (MFC)-based cooling. In case of power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3-D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is because signal, power, and thermal interconnects are all competing for routing space, and the related TSVs interfere with gates and wires in each die. We present a co-optimization methodology for signal, power, and thermal interconnects in 3-D ICs based on design of experiments (DOE) and response surface methodology (RSM). The goal of our holistic approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space exploration for early design stage. We also provide an in-depth comparison between T-TSV versus MFC-based cooling method and discuss how to employ DOE and RSM techniques to co-optimize the interconnects. Our DOE-based optimization found the optimal design point with less effort than a gradient search-based optimization.
No takes yet. Share an insight, caveat, or question.
Lee et al. (2011) studied this question.