Logic Suitability of 50-nm In0.7 Ga0.3As HEMTs for Beyond-CMOS Applications

We have experimentally studied the suitability of nanometer-scaleIn0.7Ga0.3Ashigh-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm-gate-lengthIn0.7Ga0.3AsHEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height(ΦB)and insulator thickness(tᵢₙₛ)on the logic characteristics ofIn0.7Ga0.3AsHEMTs. The best 50-nm HEMTs with the highestΦBand the smallesttᵢₙₛexhibit anION/IOFFratio in excess of10⁴and a subthreshold slope$(S)$below 86 mV/dec. These nonoptimized 50-nmIn0.7Ga0.3AsHEMTs also show a logic gate delay$(CV/I)$of around 1 ps at a supply voltage of 0.5 V, while maintaining anION/IOFFratio above10⁴, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.