Voltage contrast in integrated circuits with 100 nm spatial resolution by scanning force microscopy

A new contactless device internal test technique is introduced based on a scanning force microscope enabling dynamic voltage contrast within passivated integrated circuits. A spatial resolution below 500 nm and voltage resolution down to voltages of 0.2 V amplitude are achieved. For the first time static voltage contrast obtained with the scanning force microscope is shown on passivated integrated circuits. Potential and limits of this test technique are discussed.