A novel bipolar process technology for sidewall base contact structure (SICOS) transistors and the effects of sidewall base contact width on device characteristics are described. The sidewall window width can be precisely controlled by utilizing two-step oxidation of a sidewall surface (TOSS). Such a surface is made by using two-step etching of a silicon epitaxial layer and through the formation of two sidewall SiO/sub 2/ and two sidewall Si/sub 3/N/sub 4/ layers. The key point in the TOSS processes is the optimization of the two sidewall Si/sub 3/N/sub 4/ thicknesses. This is necessary to prevent the extension of the bird's beak to the first sidewall SiO/sub 2/ so that the sidewall window can be selectively opened and to prevent the generation of defects. By applying the TOSS processes to a SICOS transistor, the sidewall window width can be controlled as desired. As a result, the dependences of breakdown voltage, junction capacitance, cutoff frequency, and switching speed on the sidewall window width are clarified.>
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Washio et al. (1988) studied this question.
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