Surface gate and contact alignment for buried, atomically precise scanning tunneling microscopy–patterned devices

The authors have developed a complete electron beam lithography (EBL)-based alignment scheme for making multiterminal Ohmic contacts and gates to buried, planar, phosphorus-doped nanostructures in silicon lithographically patterned by scanning tunneling microscopy (STM). By prepatterning a silicon substrate with EBL-defined, wet-etched registration markers, they are able to align macroscopic contacts to buried, conducting STM-patterned structures with an alignment accuracy of ∼100nm. A key aspect of this alignment process is that, by combining a circular marker pattern with step engineering, they are able to reproducibly create atomically flat, step-free plateaus with a diameter of ∼300nm so that the active region of the device can be patterned on a single atomic Si(100) plane at a precisely known position. To demonstrate the applicability of this registration strategy, they show low temperature magnetoresistance data from a 50nm wide phosphorus-doped silicon nanowire that has been STM-patterned onto a single atomically flat terrace.