Efficient multi‐threshold voltage techniques for minimum leakage current in nanoscale technology

The influence of multi‐threshold voltage technique on reducing the leakage power in CMOS circuits at transistor level based on Nanoscale SPICE parameters is investigated in this paper. Based on Artificial Intelligence search algorithms, three new algorithms are proposed to determine the exact threshold voltage for each transistor in order to minimize the leakage current at lowest value. These algorithms are: Slack Time Search Algorithm (STS), Leakage Power Search Algorithm (LPS), Leakage and Slack Time Search Algorithm (LSS). As a result, 70% of sub‐threshold leakage current is reduced without degrading the performance. Based on 22 nm predictive SPICE parameters proposed by BSIM4, simulation results verified the validity of the proposed algorithms.