Stringer Gate FinFET on Bulk Substrate

A gate stringer normally considered parasitic is used as a subthreshold leakage suppressor in a bulk FinFET. The gate stringer remaining along the source/drain extension suppresses the formation of a sub-fin leakage path and improves the subthreshold slope. The stringer gate structure is implemented by simple process modification in the gate etch step while the other process steps are unchanged. The fabricated stringer gate FinFET shows 35% reduction in the OFF-state leakage current compared with a conventional FinFET without a retrograde well process at the expense of only 5% increase in parasitic capacitance. The power-delay product enhancement at reduced drive voltage characteristics exhibits that the stringer gate FinFET can be an attractive candidate for low standby power and subthreshold logic applications.