Identification of trapping defects in 4H-silicon carbide metal-insulator-semiconductor field-effect transistors by electrically detected magnetic resonance

In conventional Si∕SiO2-based metal oxide semiconductor devices, performance-limiting semiconductor/dielectric interface traps are localized precisely at the Si∕SiO2 boundary. The authors show that in high-quality SiC∕SiO2-based devices, this is not necessarily the case. Magnetic resonance and electrical measurements indicate that in relatively high quality 4H-SiC metal-insulator-semiconductor field-effect transistors, there exist relatively high concentrations of intrinsic deep level defect centers extending below the SiC∕SiO2 interface into the SiC bulk. The primary defect observed is almost certainly an intrinsic defect of high symmetry, most likely a silicon vacancy center.