Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin‐film transistors

The trap states at the front and back oxide interfaces and grain boundaries of polycrystalline silicon thin‐film transistors are evaluated by using electrical characteristic analysis and device simulation. First, the method for extracting the trap densities of the front and back oxide interfaces and the grain boundaries is explained as the electrical characteristic analysis. When applied to the diagnosis of actual transistor characteristics, we see that oxygen plasma treatment or vapor heat treatment effectively decreases the trap densities at the front and back oxide interfaces, and self‐heating degradation increases the trap densities at the front and back oxide interfaces. Next, we use device simulation to examine the dependence of the transistor characteristics on the trap densities. When the simulation results were similarly applied to the diagnosis of actual transistor characteristics, we see that the oxygen plasma treatment naturally reduced the trap densities at the oxide interfaces, and the plasma‐enhanced chemical‐vapor deposition of tetraethylorthosilicate increased the trap densities at the grain boundaries. In a systematic summary of these analysis results, the effects of the trap states on the transistor characteristics, the improvement method, and the causes of degradation are discussed.