Low-temperature deposition (room temperature, RT-250 °C) of high-resistivity SiO2 layers has been successfully developed on InP substrates. Complete electrical characteristics of metal-insulator-semiconductor (MIS) diodes show promising characteristics in terms of barrier height at the SiO2-InP interface and in terms of interface state distribution (NSS). Leakage current is essentially bulk limited (ρ=4×1015 Ω cm) until a high electrical field in the range 4–6 MV cm−1 and a minimum value of NSS of 2×1011 cm−2 eV−1 range is achieved, without particular surface treatment. These results show that the technique is well adapted to n-type depletion-mode MIS field-effect transistor processing.
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Plais et al. (1991) studied this question.
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