A New Polysilicon CMOS Self-Aligned Double-Gate TFT Technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.