A novel self-aligned double-gate TFT technology

In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate (TG) and bottom-gate (BG) is realized by a noncritical chemical-mechanical polishing (CMP) step. An ultrathin channel and a thick source/drain, that allow better device performance and lower source/drain resistance, are also automatically achieved. N-channel poly-Si TFTs are fabricated with maximum processing temperature below 600/spl deg/C. Metal induced unilateral crystallization (MIUC) is used for poly-Si grain size enhancement. The fabricated SADG TFT exhibits symmetrical bidirectional transfer characteristics when the polarity of source/drain bias is interchanged. The on-current under double-gate operation is more than two times the sum of that under TG and BG operation.