A Continuous-Time Δ Σ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation

This brief presents a 120-MS/s continuous-time delta-sigma analog-to-digital conversion with a dual-slope-based time-interleaved quantizer in a 0.18-μm complementary metal- oxide-semiconductor process. Excess loop delay of two sample clocks is compensated using the time information made available through interleaved channel coupling. As a result, one full clock cycle is afforded to digital-to-analog conversion dynamic element matching (DEM) operation, allowing for a digitally synthesized DEM block.