A Lean Noise-Canceling SMASH Delta-Sigma ADC in 65-nm CMOS

This paper presents a novelΔ ΣADC architecture designed to simultaneously achieve moderate to high bandwidth and high SNDR. The proposed converter builds on a sturdy MASHΔ Σtopology, where the second stage is replaced by a noise-shaping SAR (NS-SAR). Thanks to the feedforward property of the NS-SAR, the quantization noise of the first stage is effectively canceled. A novel dynamic amplifier is proposed for the first integrator, providing an improved trade-off between area, drive capability, and power consumption. In addition, a passive summation scheme that reuses the quantizer capacitor array is employed, eliminating the need for a power-hungry amplifier. Simulation results demonstrate an SNDR of 89 dB over a 500 kHz bandwidth with a power consumption of 1.73 mW, corresponding to a FOMScof 173.7 dB. Extensive simulations further confirm robust stability across PVT variations.