Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at then‐dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions withn= 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three‐variate static functions and one concerning a dynamical control system defined by a bi‐variate PWL function.