This paper describes a CMOS 7-bit flash analog-to-digital converter capable of operation at sample rates in excess of 30 megasamples per second (MSPS) with an analog bandwidth to /spl plusmn/1/2 least significant bit (Isb) of 5 MHz. The device has been realized on a 2-/spl mu/m double-layer metal CMOS process and takes advantage of the low power consumption available from CMOS logic. Circuit techniques have been employed to overcome most of the major problems inherent in flash converters and to guarantee a completely monotonic transfer function.
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Joy et al. (1986) studied this question.