Bit error rate (BER) characteristics of single electron transistor (SET) circuits have been evaluated using the Monte Carlo simulation. It has been confirmed from the simulation results that the reliability of the complementary-SET (CSET) inverter is dominated by the universal E b/N 0-BER characteristics, where E b is the bit energy, N 0 the noise power per unit frequency, and BER the bit error rate. In this paper it is determined from the E b/N 0-BER characteristics of the CSET circuit, that the CSET system based on the conventional circuit building method cannot be implemented for room temperature operations.
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Shimano et al. (1999) studied this question.
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