Low-Noise Sample-and-Hold Circuit with Charge-Sharing and Capacitance Multiplication Technology

To address the issue of noise affecting the accuracy of the SAR ADC sample-and-hold circuit in battery management chips, a low-noise sample-and-hold circuit employing a charge-sharing technique is proposed to suppress the noise from both switches and the operational amplifier. By utilizing capacitance multiplication technology, a large effective capacitance is realized with a small physical capacitor, enabling more thorough noise suppression while avoiding the layout area penalty associated with large capacitors. Through the regulation of switching timing, the system operates in a discrete-time mode, thereby preventing loop instability that may arise from a closed-loop configuration, while still fulfilling the sample-and-hold function. The capacitance multiplication circuit employs a low-noise operational amplifier, which relaxes the design requirements for the amplifier in the main ADC signal path. The proposed circuit is designed using a standard commercial 0.35 μm BCD process and verified through Cadence Virtuoso (Version: IC617) with the Spectre simulator (Version: 15.1), including transient-noise and process-temperature corner analyses. The results demonstrate that, at a sampling frequency of 20 kHz, the proposed low-noise sample-and-hold circuit for SAR ADC achieves an effective number of bits (ENOB) of 14.03 bits, a signal-to-noise-and-distortion ratio (SNDR) of 86.02 dB, and a spurious-free dynamic range (SFDR) of 91.89 dB, providing theoretical guidance for high-precision multi-cell battery management chips.