High-Quality SiO2/Si Interface Formation and Its Application to Fabrication of Low-Temperature-Processed Polycrystalline Si Thin-Film Transistor

Improvement of SiO 2 /Si interface quality and its effect on the performance of low-temperature-processed polycrystalline silicon thin-film transistors (poly-Si TFTs) are investigated. Two gate SiO 2 formation conditions for realizing the density of interface states ( D it ) at mid-gap of 1.4 × 10 11 and 4.1 × 10 10 cm -2 eV -1 were applied to a 425°C TFT fabrication process using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). By reducing D it , reduction of threshold voltage from 1.97 to 1.12 V, reduction of sub-threshold swing from 303 to 250 mV/decade and increase of mobility from 196 to 309 cm 2 V -1 s -1 were observed. The analysis of TFT characteristics indicated the decrease of both deep and shallow level trap states. As a result, not only threshold voltage and sub-threshold swing, but also the mobility of the poly-Si TFT was significantly improved. The results indicate that low-temperature process technologies for forming a high-quality SiO 2 /Si interface are important for next-generation high-performance poly-Si TFTs.