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Current-induced domain wall motion in magnetic nanowires drives the invention of a novel ultra-dense non-volatile storage device, called “racetrack memory.” Combining with magnetic tunnel junctions write and read heads, CMOS integrability and fast data access speed can also be achieved. Recent experimental progress showed that perpendicular-magnetic anisotropy (PMA) CoFeB could be a good candidate to build up racetrack memory and promise high performance like high-density (e.g., ∼1 F2/bit), fast-speed, and low-power beyond classical spin transfer torque memories. In this paper, we first present the design of PMA CoFeB racetrack memory and a spice-compatible model to perform mixed simulation with CMOS circuits. Its area, speed, and power dissipation performance has been simulated and evaluated based on different technology nodes.
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Zhang et al. (2012) studied this question.
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