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Simulation study demonstrates reduced area and latency in quantum-dot cellular automata XOR circuits, highlighting viable alternatives to conventional silicon technology.
The continuous scaling limitations of semiconductor technology based on Complementary Metal-Oxide-Semiconductors (CMOS) have motivated the search for alternative nanotechnologies capable of delivering higher performance with lower power consumption. Quantum-dot Cellular Automata (QCA) has emerged as a promising paradigm, offering extremely low power dissipation, nanoscale device density, and high switching speeds. This paper introduces a novel design of XOR gates in QCA, developed using the principle of reduced distance-based cell connections to minimize area and latency. The proposed architecture eliminates wire crossovers and enhances layout efficiency, thereby improving manufacturability and robustness. Additionally, Gray code communication and Vedic multiplication modules are designed and implemented using the proposed XOR configuration to demonstrate its versatility in arithmetic and communication applications. Vedic multiplication, being a fundamental logical building block in modern digital systems, benefits significantly from the compact and energy-efficient XOR gate design. The simulation results, carried out using the QCADesigner tool, confirm that the proposed designs outperform existing XOR-based implementations in terms of cell count, area utilization, and propagation delay. The improved results highlight the potential of QCA as a viable replacement for CMOS in the realization of efficient logic architectures for next-generation nanoelectronic systems. This work contributes to advancing QCA-based digital circuit design by addressing crossover challenges and optimizing resource utilization, thereby paving the way for scalable and practical implementations in future computing and communication systems.
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Bhuvaneswari et al. (2026) studied this question.
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