The distributions of carriers and internal electric fields have been calculated and compared for five different transistors. The doping profile underneath the 1 μm gate, the gate width and the positions of the source and the drain relative to the gate are the same for all devices. The stray fields from the metai gate in all transistors have been introduced to study the effect of gate trench shape and metallisation on the carriers and internal fields. We find that these stray fields improve the planar FET with respect to noise performance, while the edges of the gate trench counteract the effects of the gate metallisation. Some AC characteristics have been discussed in the view of the internal fields. For two devices, the calculations have been repeated with an n-type buffer layer inserted between the epilayer and the intrinsic substrate. This buffer was found to have much the same effect on the distributions of fields and carriers as the gate stray field had. We conclude that the gate metallisation stray field or the substrate buffer can improve the performance of the transistor, and they represent an important additional design criterion.
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C. Moglestue (1984) studied this question.
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