Low-Power, High-Sensitivity Readout Integrated Circuit With Clock-Gating, Double-Edge-Triggered Flip-Flop for Mid-Wavelength Infrared Focal-Plane Arrays

To facilitate a high-dynamic-range operation of mid-wavelength infrared focal-plane arrays, a low-power, high-sensitivity readout integrated circuit (ROIC) is proposed. In this ROIC, the capacitor-reset block employing clock signals adopts a double-edge-triggered flip-flop instead of a single-edge-triggered one to reduce errors within the final output signals. In addition, an asynchronous clock-gating technique is employed to control clock-signal usage in accordance with the input signal, thereby reducing the power consumption within two-dimensional arrays. The proposed low-power, high-sensitivity ROIC has been realized with a 0.18-μm 1-poly 6-metal CMOS process. It has been confirmed that in cases involving low input-signal current, the power consumption of the proposed ROIC can be reduced to approximately 2% of that of conventional ROICs.