An on-chip vertical solenoid inductor design for multigigahertz CMOS RFIC

This paper presents a compact and high-quality on-chip vertical solenoid inductor design. By taking advantage of an ever increasing number of metal layers in the modern CMOS process, the proposed structure can continuously reduce the inductor area and increase the quality factor (QF) and self-resonant frequency (SRF). Experimental results show that, compared to the 4.1-nH planar spiral inductor using a six-metal layer process, the 4.8-nH vertical solenoid inductor approximately gives a 20% increase in the maximum QF and 50% increase in the SRF, but only occupies 20% of the area. A detailed design methodology for the optimal inductor geometry will be explained. Using a standard six-metal layer CMOS process, simulation results indicate that an inductor with a 40-/spl mu/m radius and 10-/spl mu/m metal width should be used for an amplifier load, which requires 30% frequency tuning range at 5.2 GHz. An additional 7.8-dB signal gain can be obtained if the frequency tuning range requirement is reduced by one-half. Furthermore, to help the designers' decision, contour plots will be presented as a guideline. Lastly, several design guidelines will be presented.