A 3-V 230-MHz CMOS decimation subsampler

The use of subsampling for frequency downconversion and related tradeoffs in radio receivers are discussed. It is found that using the highest possible sampling frequency both relaxes anti-alias filtering requirements and reduces the effect of clock jitter. However, high-speed switched-capacitor circuits are difficult to design and they are typically power consuming. A switched-capacitor decimation sampler is proposed as a way to achieve more optimal sampling frequencies both at the input and the output of the sampler. The design and experimental results of a 3-V 230-MHz CMOS decimation subsampler are presented. The sampler achieves an input referred noise density of 44 nV//spl radic/Hz, an IIP/sub 3/ of +19.5 dBV, and a -52-dBc worst mixing product from clock skew with a 200-MHz input.