High‐efficiency CMOS stacked‐FET power amplifier for W‐CDMA applications using SOI technology

A linear CMOS power amplifier (PA) is developed for wideband code‐division multiple‐access (W‐CDMA) application using 0.18 µm silicon‐on‐insulator (SOI) technology. By adopting a quadruple‐stacked FET structure, 1W of output power is achieved at 4V supply voltage. A negative capacitance circuit is employed to maximise the efficiency of the PA by cancelling out the excessive capacitance at the source terminal of the common‐gate stage. Besides, a lineariser based on the variable capacitor circuit is added to reduce the inherent AM‐PM distortion of the CMOS FET. Using W‐CDMA modulation at 837MHz, the fabricated PA module delivers a PAE of 47.5% and an adjacent channel leakage ratio of − 36dBc at the output power of 27.1dBm.