A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-/spl mu/m high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz cutoff frequency is fabricated together with 1.3-/spl mu/m CMOS. A variable-impedance data-line load, a common data-line equalizing circuit, and a sense-amplifier selection technique together achieve a 7-ns access time. Gates combining bipolar and CMOS devices achieve a power dissipation of one-third that of conventional bipolar 64-kb ECL RAMs.
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Miyaoka et al. (1987) studied this question.