10 Gbit/s timing recovery circuit using dielectric resonator and active bandpass filters

A clock recovery circuit that employs a dielectric resonator, designed for the 10.368Gbit/s demonstrator of the R1051 RACE project is described. Experimental results have shown a jitter performance and sensitivity to detuning well within usual specifications for practical links. This circuit thus provides a very attractive low cost solution for multigigabit transmission.