Towards a controlled patterning of 10 nm silicon gates in high density plasmas

This article demonstrates that a 10 nm isolated silicon pattern on a very thin gate can be achieved if the plasma parameters and chemistry that impact the critical dimension (CD) control are well understood. The parameters investigated are the passivation layers that form on the silicon gate sidewalls which directly impact the CD control, the nature of the mask used during the gate process (resist mask or SiO2 hard mask), the charging effects developed when the plasma lands on a thin gate oxide.