A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor

The six-issue integer datapath of the second-generation Itanium microprocessor is described. Pulse techniques enable a high-speed, 20-ported, 128-entry, 65 bit register file with only 12 wordlines per register. A four-stage operand bypass network achieves a fully bypassed design with operands sourced from 34 locations with 16 destinations. To control this network, over 280 bypass comparators are utilized. Using half a clock for execution and half a clock for bypass, each result is available for the next instruction. Functional units are pre-enabled, reducing power consumption by 15% while eliminating a stage of result mixing and improving performance. The part is fabricated in a six-layer 0.18 /spl mu/m process and operates at 1.0 GHz at 1.5 V, consuming less than 130 W in about 420 mm/sup 2/.