An MOS current conveyor design suitable for VLSI implementation is described. It uses a new circuit architecture which allows for low supply voltage operation at 3V enhancing its application versatility as a standard cell in VLSI analogue IC design as well as in mixed-mode IC design.
No takes yet. Share an insight, caveat, or question.
Cheng et al. (1993) studied this question.
Synapse has enriched 3 closely related papers on similar clinical questions. Consider them for comparative context: