Intermediate Oxide Formation in Double‐Polysilicon Gate MOS Structure

An intermediate insulator formation technique is realized using the concentration‐dependent oxidation (CDO) of the phosphorus‐doped first polysilicon gate. Utilizing the CDO effect, that is, heavily doped Si is oxidized faster than lightly doped Si, a thick intermediate oxide is formed to cover the first gate with its own oxide and a substrate surface to form the second gate oxide with simultaneous wet oxidation at 700°–900°C. Electrical properties of the intermediate insulator are discussed in terms of the formation conditions and topographical structures of the overlapped region. It is found that oxidation temperatures of around 900°C and moderate oxide thicknesses produce superior electrical properties and preferable geometries. In response to these requirements a dry‐wet‐dry oxidation (D‐W‐D) technique is successfully developed. A 5‐17‐5 min D‐W‐D oxidation at 900°C causes a 50 nm oxide to be formed on single crystal (100) silicon and a 210 nm oxide on the phosphorus‐doped polysilicon. The autodoping effect of phosphorus atoms incorporated in the polysilicon gate is also discussed. It gives rise to harmful threshold voltage lowerings for the second gate n‐channel transistors.