Closed-Loop Pole Analysis via Output Impedance in Miller-Compensated Amplifiers

A closed-loop pole analysis (CLPA) method is presented for Miller-compensated multistage amplifiers. CLPA broadens design-oriented analysis by adopting an impedance-based point of view, directly relating T/(1+T) to closed-loop response, along with clear circuit design specifications (gm2, Ro2, Cp2and gm3), offering intuitive and quantitative design insights. Specifically, CLPA modeling the inner Miller loop as a second-order RLC cell allows natural frequency and damping to be extracted from output impedance breakpoints. Leveraging this connection, a resonance control scalable single-Miller capacitor compensation (RCSMC) topology is developed. Measurement results in 28nm CMOS show that a three-stage RCSMC amplifier achieves 124 dB DC gain, a 1.16MHz gain-bandwidth product, and an FOM1of 39,456MHz·pF/(μW·mm2) with a 200 pF load, while simulations of a four-stage RCSMC amplifier reach 120 dB gain and an FOM1of 1,137,800MHz·pF/(μW·mm2) for a 64 nF load, demonstrating performance and scalability.