A Power-Optimal Design Methodology for High-Resolution Low-Bandwidth SC ΔΣ Modulators

In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor ΔΣ modulators (ΔΣMs) is presented. The most power-efficient ΔΣ architecture is identified among single-loop feedback and feedforward topologies with different loop ordersN, oversampling ratiosOSR, and quantizer resolutionsB. Based on this study, an experimental prototype has been implemented in a 0.18- μm CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidthfBWof 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 μW from a 1.8-V supply.