In this work, we develop a comprehensive model of the total gate capacitance (CG) of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance (Cins) and the inversion capacitance (Cinv). The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we compare the CG/Cinsratio with that of double-gate (DG) transistors and study the degradation of the total gate capacitance of both devices as a function of the gate voltage and device size. It is shown that the CG/Cinsratio is higher in DGs, particularly for very small devices.
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Ruiz et al. (2010) studied this question.
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