Bias Stress Stability Improvement in Solution-Processed Low-Voltage Organic Field-Effect Transistors Using Relaxor Ferroelectric Polymer Gate Dielectric

Low-voltage organic-field effect transistors (OFETs) using relaxor ferroelectric polymer poly (vinylidene fluoridetrifluoroethylene-chlorofloroethylene) P (VDF-TrFE-CFE)) were fabricated. The measured hysteresis loop and the threshold voltage shift under negative bias stress (NBS) are opposite to that of the reference device using low-k CYTOP gate dielectric layer, in which the hysteresis and NBS-induced instabilities are explained by gate bias-induced charge trapping. The anomalous behaviors in the P (VDF-TrFE-CFE) OFETs are attributed to the stress-induced remnant polarization in P (VDF-TrFE-CFE), which induces additional mobile charges into the channel. By adding a thin CYTOP layer between the P (VDF-TrFE-CFE) layer and the semiconductor layer, the two effects of charge trapping and remnant polarization under gate bias are found to be neutralized with each other, resulting in low-voltage OFETs of negligible hysteresis and excellent NBS stability.