Orientation effect reduction through capless annealing of self-aligned planar GaAs Schottky barrier field-effect transistors

A reduction in the orientation effect on self-aligned ion-implanted planar GaAs Schottky barrier field-effect transistors (FET’s) has been found. The FET’s were fabricated using capless annealing to avoid thermal stress that occurs at a dielectric/GaAs interface during capped annealing. Both mean and standard deviation in FET threshold voltage as a function of gate length are compared for FET’s oriented in the two perpendicular [110] directions. Very little orientation dependence is observed. Similar high-speed switching operation is also found for either orientation. These results indicate that stress-enhanced preferential lateral diffusion which appears to be a major factor in the orientation effect can be reduced through capless annealing.