100-nm-size ferroelectric-gate field-effect transistor with 108-cycle endurance

The fabrication process of 100-nm-size ferroelectric-gate field-effect transistors (FeFETs) with high endurance was reported. The FeFETs had Pt/Sr 0.8 Ca 0.2 Bi 2 Ta 2 O 9 (SCBT)/HfO 2 /Si stacks where the Pt gate length was 100 nm. The FeFETs were successfully fabricated by integrating many technologies such as fine patterning of etching masks by electron-beam lithography, precise anisotropic etching of the gate stacks, well-controlled ion implantation for gate-self-aligned sources and drains, and the sidewall-cover process that we had developed. Good performances of the FeFETs were characterized by the endurance of 10 8 program-and-erase cycles with negligible threshold-voltage shift and good drain-current retention for 3.98 × 10 5 s.