Memristor: Part II–DC, Transient, and RF Analysis

The dc and RF circuit performance of memristor circuits, including transient behavior, is developed by considering current contributions arising from different conduction mechanisms, namely, filament-assisted and bulk tunneling currents and currents flowing through low and high conductivity filaments. The dc circuit model explains the observed I-V hysteresis and most importantly allows scaling and optimization. A transient circuit model of memristive system is developed, based upon the dynamics, incorporating underlying electrochemistry that suggests SET and RESET transitions for a 50-nm TiO2-based memristor take approximately 120 ps to stabilize. A faster READ/WRITE operation would require appropriate conditioning circuitry. RF analysis suggests for a maximum allowable frequency of 7.5 GHz beyond which memristors can no longer be used as RRAM. These values can be pushed to higher limits by increasing the device cross-sectional area or choosing lower permittivity materials. The developed model allows its incorporation in commercial circuit simulators. The derived model is validated by incorporating it in Chua's chaotic circuit.