Optimum Ferroelectric Film Thickness in Metal–Ferroelectric–Insulator–Semiconductor Structures Composed of Pt, (Bi,La)4Ti3O12, HfO2, and Si

The optimum ferroelectric film thickness in metal–ferroelectric–insulator–semiconductor (MFIS) structures is investigated, in which 80- to 560-nm-thick (Bi,La) 4 Ti 3 O 12 (BLT) films are deposited on HfO 2 buffer layers using a sol–gel spin-coating method. It is found from electrical characteristics of MFIS diodes as well as MIS diodes that the HfO 2 layers act as excellent barriers for suppressing both leakage current and atom interdiffusion when they are annealed in a rapid-thermal-annealing furnace at 900 °C for 1 min in O 2 flow. In MFIS diodes, the memory window width in capacitance–voltage ( C – V ) characteristics is found to increase from 0.2 to 1.6 V, as ferroelectric film thickness increases from 80 to 560 nm. On the basis of these results, the relationships among memory window width, ferroelectric film thickness, and the optimum applied voltage are discussed. Finally, it is shown from the capacitance change measured over 24 h that data retention characteristics are excellent in samples with BLT films thicker than 240 nm.