A solid-state sampling circuit for use at low pulse repetition frequencies

A solid-state sampling circuit (`boxcar integrator') is described which has a ratio of holding time to learning time in excess of 10 11 . The circuit may be used to improve the signal-to-noise ratio for signals having repetition frequencies between 500 and 10 −4 pulses per second or to sample a 200 ns portion of a single event and hold the sample to within 1% for 6 h. It accepts positive or negative signals of up to 5 v amplitude, has unity gain and has an overall linearity of better than ±0·1%.