Improvement in the negative bias illumination temperature stress instability of In–Ga–Zn–O thin film transistors using an Al2O3 buffer layer

The negative bias illumination temperature stress (NBITS) instability of amorphous In–Ga–Zn–O thin film transistors with SiO2 and SiO2/Al2O3 gate dielectric layers was evaluated. The introduction of a thin Al2O3 layer between the channel and SiO2 layer decreased the threshold voltage shift (ΔVth) by ∼20% after a NBITS for 1000 s. The interfacial trap density of the two samples, estimated by conductance and off‐current measurements, were almost identical. The higher valence band offset (∼0.4 eV) at the Al2O3/In–Ga–Zn–O interface compared to the SiO2/In–Ga–Zn–O interface decreased the gate leakage current and bulk trapping of holes under illumination. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)