Performance of state regulator systems with floating-point computation

The performance of a digital state regulator system having an A/D converter of finite wordlength and a floating-point estimator/ controller computer of finite mantissa-length is analyzed. An upper bound on the mean-square state error, as a function of the two wordlengths, is derived in closed form. This bound can be used in analyzing the stability of open-loop unstable systems and to give insight into the error-performance/hardware-cost tradeoff for wordlength design choices. An example is given where the estimates of error performance of a second-order digitally-regulated plant, as estimated from the upper bound, from the system covariance equation, and from simulation are compared.