Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability

We present a model for estimating the impact of gate line edge roughness (LER) on the performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG FinFETs are investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length (xi), rms amplitude or standard deviation (sigma) of the line edge from its mean value, and roughness exponent ( alpha). Our approach provides physical insight into how LER impacts FinFET performance. In addition, our modeling approach is more efficient than Monte Carlo TCAD simulations and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Furthermore, a spacer-defined gate electrode (versus a resist-defined gate electrode) provides for reduced variability in performance, indicating that the gate length mismatch has more impact than lateral offset between the front and the back gates.