A 31.25 MHz Bandwidth 52.4 dB SNDR VCO-Based ADC With on-Chip Non-Linearity Correction

This paper presents a method for correcting nonlinearities in voltage-controlled oscillator (VCO) based analog-to-digital converters (ADCs). The proposed approach utilizes a simple digital logic circuit, three single-stage transistor-based circuits, and four switches to enhance the linearity of the VCO tuning curve. The prototype is designed in 65-nm CMOS process with a supply voltage of 1.2 V and measurements have demonstrated that the pseudo-differential VCO-based ADC achieves 2.5-bit improvement in the Effective Number of Bits (ENOB), with only marginal increases of 5.2% and 9% in total power and area, respectively.