Behavior of tellurium on silicon (100)

The adsorption of tellurium on Si(100) was investigated using scanning tunneling microscopy (STM) and LEED. Tellurium was evaporated onto the clean silicon (100)2 × 1 surface at ≈ 25°C. Coverages ranging from 0.1 to 3.0 ML were investigated. Atom-resolved images reveal that low coverages of Te deposited at room temperature adsorb on top of the silicon 2 × 1 dimer rows with a minimum spacing of 2a where a = 3.84 Å is the width of a 1 × 1 surface unit cell. There is a slight preference for growth along the silicon dimer rows. This surface saturates at 0.25 ML. When the low coverage sample is subsequently annealed for 10 min at 300°C, trenches perpendicular to the silicon dimer rows appear with tellurium decorating the trench edge. At ⩾ 1 ML Te coverage, the surface consists of rows of Te with a spacing of a with missing rows of atoms at a maximum interval of 5–6 rows.