Real-time FPGA prototyping of joint blind equalization with ZF-NL-RSSE for data center interconnects

To maximize power efficiency and system simplicity, blind equalization is widely utilized in high-speed intensity modulation/direct detection (IM/DD) systems, enabling the cost-efficient deployment in data center interconnects (DCI). Meanwhile, recognized as the theoretically optimal equalizer, maximum likelihood sequence estimation (MLSE) is recommended for broad implementation, particularly in high-speed IM/DD systems. However, conventional MLSE faces challenges due to its inability to blindly estimate both linear and nonlinear channel distortions, coupled with its high implementation complexity. This Letter proposes and experimentally demonstrates a joint blind equalization scheme featuring zero-forcing nonlinear reduced-state sequence estimation (ZF-NL-RSSE) in a real-time 80-Gbps PAM-4 transmission system based on an FPGA chip. Experimental results show that over 5-km single-mode fiber (SMF) transmission, the ZF-NL-RSSE scheme achieves rapid blind convergence, attaining a BER performance superior to traditional FFE and VDFE and comparable to the full-state ZF-NL-MLSE, while significantly lowering computational complexity.